The present invention relates to a thin film transistor substrate for use in active matrix liquid crystal display devices or self-emission type display devices such as organic light emitting devices and the like, and especially a thin film transistor substrate using the low temperature polycrystalline Si technique, and a process for producing the same.
In liquid crystal displays, not only the pixel switches but also circuits are formed on a substrate by using thin film transistors using a polycrystalline Si film which can be formed at a low temperature not higher than the heat-resistant temperature of glass, in order to reduce the number of parts and lower the cost. In the thin film transistor using a polycrystalline Si film and especially in the N type thin film transistor, it is usual to provide areas of LDD (lightly doped drain) between the source and the drain and gate, in order to improve the reliability. As a method for forming LDD without positional deviation from the gate, JP-A-5-152325 has disclosed a process of side-etching the electrically conductive film constituting the gate to form the gate into a shape retrograding from the resist, and forming an LDD on the semiconductor film provided under the retrograding region in a self-aligned manner with the gate.
In a liquid crystal display, the electrically conductive film constituting the gate is simultaneously used as a scan signal line, too, and therefore it is required to have a low resistivity enough to decrease the retardation in the transmission of signal via the line. Since the liquid crystal display using a thin film transistor using polycrystalline Si as a semiconductor film is exposed to a high temperature at the time of activating the dopant, the gate is simultaneously required to be resistant to heat. In JP-A-11-163366, there has been disclosed an example in which the gate is formed of molybdenum (Mo) and a molybdenum-tungsten (W) alloy (hereinafter, simply referred to as Moxe2x80x94W alloy) having a low resistance and a high heat resistance and the LDD is formed in a self-aligned manner by a process including resist ashing.
In the gate processing of thin film transistor composed of Moxe2x80x94W alloy, a dry etching method or a wet etching method can be used, among which wet etching method is advantageous from the viewpoint of productivity because a higher etching rate can be adopted in the wet etching method. However, in the wet etching of Mo alloy, a passivation film can be formed on the film surface depending on the conditions of etching, such as stirring condition, and thereby the etching rate can vary, as mentioned in JP-A-10-247733. Accordingly, in the production process of side-etching a Moxe2x80x94W film by the wet-etching method and thereby forming LDD in a self-aligned manner in the sites retrograding from the resist, there has been a problem that reflection of the variation in the etching rate brings about an unevenness in the length of side-etching and further the length of LDD, due to which the characteristic properties of thin film transistors become uneven and the product yield decreases.
It is an object of the present invention to provide a thin film transistor substrate high in productivity and exhibiting uniform characteristic properties, and to a process for producing the same.
The present invention provides a thin film transistor substrate comprising coplanar type thin film transistors on a transparent insulating substrate, said thin film transistor having a semiconductor film made of crystalline silicon, a gate insulator film formed on the semiconductor film, a gate made of a metallic film and formed on the gate insulator film, a source and a drain both prepared by doping the semiconductor film and placed so as to hold the gate between them, LDD regions which are doped with a dopant of the same type as used for the source and drain at a lower concentration than in the source and drain being formed at the edges of the gate,
wherein said gate is made of a mono-layered metallic film composed mainly of Mo and containing W in an amount not smaller than 5% by weight and smaller than 25% by weight.
The present invention further provides a process for producing the above-mentioned thin film transistor substrate which comprises a step of processing a gate with an etching solution containing phosphoric acid in an amount not smaller than 60% by weight and not larger than 70% by weight.